IEEE 1149.10 : 2017
IEEE 1149.10 : 2017
HIGH-SPEED TEST ACCESS PORT AND ON-CHIP DISTRIBUTION ARCHITECTURE
Institute of Electrical & Electronics Engineers
Table of Contents
1. Overview
2. Normative references
3. Definitions, abbreviations, acronyms, and
special terms
4. High-speed test access port (HSTAP)
5. Packet encoder/decoder and distribution
architecture
6. Packet definitions
7. BSDL definitions
8. Channel bonding
9. PDL
10. Compliance verification
Annex A (informative) - Bibliography
Abstract
Specifies a high speed test access port for delivery of test data, a packet format for describing the test payload, and a distribution architecture for converting the test data to/from on-chip test structures.
General Product Information
| Document Type | Standard |
| Status | Current |
| Publisher | Institute of Electrical & Electronics Engineers |
