IEEE 1800.2 : 2017
IEEE 1800.2 : 2017
UNIVERSAL VERIFICATION METHODOLOGY LANGUAGE REFERENCE MANUAL
Institute of Electrical & Electronics Engineers
Table of Contents
1. Overview
2. Normative references
3. Definitions, acronyms, and abbreviations
4. UVM class reference
5. Base classes
6. Reporting classes
7. Recording classes
8. Factory classes
9. Phasing
10. Synchronization classes
11. Container classes
12. UVM TLM interfaces
13. Predefined component classes
14. Sequences classes
15. Sequencer classes
16. Policy classes
17. Register layer
18. Register model
19. Register layer interaction with RTL
design
Annex A (informative) - Bibliography
Annex B (normative) - Macros and defines
Annex C (normative) - Configuration and resource
classes
Annex D (normative) - Convenience classes, interface,
and methods
Annex E (normative) - Test sequences
Annex F (normative) - Package scope functionality
Annex G (normative) - Command line arguments
Abstract
Defines the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments.
General Product Information
| Document Type | Standard |
| Status | Current |
| Publisher | Institute of Electrical & Electronics Engineers |
