IEEE 1149.7 : 2009

IEEE 1149.7 : 2009

REDUCED-PIN AND ENHANCED-FUNCTIONALITY TEST ACCESS PORT AND BOUNDARY-SCAN ARCHITECTURE

Institute of Electrical & Electronics Engineers

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Table of Contents

1. Overview
2. Normative references
3. Definitions, acronyms, and abbreviations
4. TAP.7 concepts and architecture
5. T0-T3 TAP.7 operational overview
6. T4-T5 TAP.7 operational overview
7. System concepts
8. TAPC hierarchy
9. Registers, commands, and scan paths
10. RSU ancillary services
11. RSU Online/Offline capability
12. TAP signals
13. TDO(C) Signal Drive Policy
14. TMS(C) Signal Drive Policy
15. IEEE 1149.1-compliance concepts
16. T0 TAP.7
17. Extended concepts
18. T1 TAP.7
19. T2 TAP.7
20. T3 TAP.7
21. Advanced concepts
22. APU Scan Packets
23. T4 TAP.7
24. MScan Scan Format
25. OScan Scan Formats
26. SScan Scan Formats
27. T5 TAP.7
28. Transport operation and interfaces
29. Test concepts
30. Documenting IEEE 1149.7 test endpoints (BSDL.7)
31. Documenting IEEE 1149.7 test modules (HSDL.7)
Annex A (informative) - IEEE 1149.1 reference material
Annex B (informative) - Scan examples in timing diagram form
Annex C (informative) - Scan examples in tabular form
Annex D (informative) - Programming considerations
Annex E (informative) - Recommended electrical characteristics
Annex F (informative) - Connectivity/electrical recommendations
Annex G (informative) - Utilizing SScan Scan Formats
Annex H (informative) - The RTCK signal
Annex I (informative) - Bibliography

Abstract

Specifies a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001.

General Product Information

Document Type Standard
Status Current
Publisher Institute of Electrical & Electronics Engineers

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