COMMON TEST INTERFACE PIN MAP CONFIGURATION FOR HIGH-DENSITY, SINGLE-TIER ELECTRONICS TEST REQUIREMENTS UTILIZING IEEE STD 1505[TM]
Institute of Electrical & Electronics Engineers
1 Overview
2 Normative references
3 Definitions, acronyms, and abbreviations
4 Common test interface requirements
Annex A (normative) - Common test interface signal
definitions for pin map
Annex B (informative) - Bibliography
Annex C (informative) - IEEE List of Participants
Pertains to military and aerospace automatic test equipment (ATE) testing applications.
| Document Type | Standard |
| Status | Current |
| Publisher | Institute of Electrical & Electronics Engineers |
