STANDARD SIGNALLING METHOD FOR A BIDIRECTIONAL PARALLEL PERIPHERAL INTERFACE FOR PERSONAL COMPUTERS
Institute of Electrical & Electronics Engineers
1. Overview
1.1 Scope
1.2 Purpose
2. References
3. Definitions
3.1 General terminology
3.2 Communication modes
3.3 Operating phases
4. Features and compliance
4.1 Interface overview
4.2 Features
4.3 Device compatibility criteria
4.4 Device compliance criteria
4.5 Cable compliance criteria
5. Interface signals
5.1 HostClk/nWrite (nStrobe): host driven
5.2 AD1...AD8 (Data1...Data8)
5.3 PtrClk/PeriphClk/Intr (Intr(nAck): peripheral driven
5.4 PtrBusy/PeriphAck/nWait (busy): peripheral driven
5.5 AckDataReq/nAckReverse (PError): peripheral driven
5.6 Xflag (Select): peripheral driven
5.7 HostBusy/HostAck/nDStrb (nAutoFd): host driven
5.8 Peripheral Logic High: peripheral driven
5.9 nReverseRequest (nInit): host driven
5.10 nDataAvail/nPeriphRequest (nFault): peripheral driven
5.11 1284 Active/nAStrb (nSelectIn): host driven
5.12 Host Logic High: host driven
6. Interface concepts
6.1 Link level and data level separation
6.2 IEEE 1284 communication options
6.3 Nibble Mode/Byte Mode transfer
6.4 Host-initiated transfers
6.5 Peripheral-initiated transfers
6.6 Multiple byte transfers
6.7 Interface errors
6.8 Peripheral error resolution
6.9 ECP Mode command/data
6.10 EPP Mode addressing
6.11 Device identification
7. Interface operation
7.1 Power-on
7.2 Initialization
7.3 Compatibility
7.4 Negotiation
7.5 Peripheral-to-host transfer modes
7.6 Device ID
7.7 Termination
7.8 Collisions
8. Mechanical and electrical interface
8.1 General considerations
8.2 Mechanical characteristics
8.3 Electrical characteristics
9. Software support
9.1 General considerations
9.2 Application level compatibility
9.3 MS-DOS IEEE 1284 driver
9.4 Windows 1284 driver
9.5 Reverse channel data
9.6 Link performance
ANNEX
A. (normative) Timing specifications
B. (normative) Signal transition events
C. (informative) Centronics and PC-compatible parallel
interfaces
D. (informative) Bibliography
E. (informative Reducing data loss in ECP reverse
termination
Gives a signaling method for asynchronous, fully interlocked, bidirectional parallel communications between hosts and printers or other peripherals.
| Document Type | Standard |
| Status | Current |
| Publisher | Institute of Electrical & Electronics Engineers |
| Supersedes |
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